`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/31 09:59:56
// Design Name: 
// Module Name: compa
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module compa
    #(parameter width = 32)
    (
        input logic [ 3: 0]         branch_type,
        input logic [width-1:0]     src_0,
        input logic [width-1:0]     src_1,

        output logic res
    );

    always_comb begin
        res = 0;        
        case(branch_type)
            4'b0000:    begin   //beq
                res = (src_0 == src_1);
            end
            4'b0001:    begin   //bne
                res = (src_0 != src_1);
            end
            4'b0010:    begin   //bgez
                res = (!src_0[31]);
            end
            4'b0011:    begin   //bltz
                res = (src_0[31]);
            end
            4'b0100:    begin   //bgezal
                res = (!src_0[31]);
            end
            4'b0101:    begin   //bltzal
                res = (src_0[31]);
            end
            4'b0110:    begin   //bgtz
                res = (!src_0[31]&&(src_0 != 32'b0));
            end
            4'b0111:    begin   //blez
                res = (src_0[31]|src_0 == 32'b0);
            end
        endcase
    end
    
endmodule
